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[Windows Develop] USB-slavefifo

Description: 本组程序包括FPGA程序，固件程序和上位机程序，实现USB的数据传输功能，采用Slave Fifo模式，上位机程序利用Cypress公司提供的库函数进行开发-In this group include FPGA, firmware, procedures and PC procedures realize USB data transfer function, the Slave Fifo mode, host computer program using Cypress library functions provided by the company to develop
Platform: | Size: 5099520 | Author: 林颖 | Hits:

[VHDL-FPGA-Verilog] asynch_fifo

Description: FPGA VERILOG 用DCFIFO实现 跨时钟域的数据传输，已验证，直接可用-FPGA VERILOG using DCFIFO realize cross-clock domain data transfer, has been verified, directly available
Platform: | Size: 1028096 | Author: alison | Hits:

[VHDL-FPGA-Verilog] FIFO_Example2

Description: 用Verilog语言写的FPGA FIFO，仅供参考。-Verilog language used to write the FPGA FIFO, for informational purposes only.
Platform: | Size: 1024 | Author: yangyu | Hits:

[VHDL-FPGA-Verilog] usbin_v1.7

Description: 用于cy7c68013与fpga的从FIFO通讯.版本1.7-For the CY7C68013 and FPGA communications from the FIFO. Version 1.7
Platform: | Size: 2048 | Author: | Hits:

[VHDL-FPGA-Verilog] FPGA_FIFO

Description: 使用Verilog编写的同步FIFO，可通过设置程序中的DEPTH设置FIFO的深度，FIFO_WRITE_CLOCK上升沿向FIFO中写入数据， FIFO_READ_CLOCK上升沿读取数据。本程序对FIFO上层操作简单实用。-Prepared by the use of Verilog synchronous FIFO, through the setup program in the FIFO depth DEPTH settings, FIFO_WRITE_CLOCK rising edge to the FIFO write data, FIFO_READ_CLOCK rising edge of read data. This procedure on the upper FIFO operation simple and practical.
Platform: | Size: 1024 | Author: 张键 | Hits:

[VHDL-FPGA-Verilog] connect20090223

Description: fpga从FIFO读数据并上传到双口ram中。-FPGA read data from the FIFO and upload it to dual-port ram Medium.
Platform: | Size: 468992 | Author: 张菁 | Hits:

[TCP/IP stack] CCD

Description: CCD数字相机的全代码，DMA方式读取FPGA，FIFO送入计算机，网口跑UDP协议-CCD digital camera the entire code, DMA mode to read FPGA, FIFO into the computer, I run UDP network protocol
Platform: | Size: 40960 | Author: ccdd | Hits:

[VHDL-FPGA-Verilog] fifo

Description: 异步fifo，用Verilog编写，包含testbench，已经通过modelsim调试，内含文档和波形图-Asynchronous fifo, to prepare to use Verilog, including testbench, debug modelsim has passed, including documents and wave
Platform: | Size: 40960 | Author: iechshy1985 | Hits:

[VHDL-FPGA-Verilog] xapp460

Description: 利用FPGA实现TMDS接口标准，可用于DVI以及HDMI接口的FPGA实现（含文档）-Video Connectivity Using TMDS I/O in Spartan-3A FPGAs
Platform: | Size: 1594368 | Author: wicky | Hits:

[VHDL-FPGA-Verilog] fifo_test.v.tar

Description: code for implementing high speed fifo for apturing data from fpga-code for for implementing high speed fifo for apturing data from fpga
Platform: | Size: 2048 | Author: Vikas | Hits:

[ARM-PowerPC-ColdFire-MIPS] fifo

Description: 用FPGA做的fifo，源码，调试通过，有工程和波形文件-FPGA to do with the fifo, source code, debugging through, there are engineering and waveform file
Platform: | Size: 354304 | Author: 马泽龙 | Hits:

[VHDL-FPGA-Verilog] fifo

Description: 使用Altera公司的FPGA进行VHDL开发。使用quartus2 9.0软件在EP1C3T144C8开发板上实现先进先出的队列。-The use of Altera' s FPGA-VHDL development. Use quartus2 9.0 software EP1C3T144C8 Development Board to achieve FIFO queue.
Platform: | Size: 164864 | Author: Daisy | Hits:

[Software Engineering] AsynchronousFIFOArchitectures-CN

Description: AsynchronousFIFOArchitectures，这篇经典FPGA-FIFO文章的中文版-AsynchronousFIFOArchitectures, this classic FPGA-FIFO Chinese version of the article
Platform: | Size: 545792 | Author: energy | Hits:

[Other] FIFO

Description: fifo的实现，可以作用于memory的数据传输等地方，在fpga上实现，可以进行综合和仿真-fifo implementation, you can act on memory data transfer and other places, in the fpga to achieve, to undertake a comprehensive and Simulation
Platform: | Size: 6144 | Author: zz | Hits:

[VHDL-FPGA-Verilog] FIFO

Description: 设计了一个具有双时钟信号，双复位信号的FIFO，用于FPGA中的数据缓冲，RAM的定义是参数型，可以根据自己的需求，修改此参数，完成RAM的容量扩展。程序中有详细的说明-Designed a dual-clock signal, double reset signal FIFO, for the FPGA in the data buffer, RAM is defined as parameter type, according to their needs, and modify this parameter, the completion of the capacity expansion of RAM. Procedures described in detail
Platform: | Size: 183296 | Author: luosheng | Hits:

[VHDL-FPGA-Verilog] sdcard_mass_storage_controller_latest.tar

Description: 基于wishbone总线的SD Card IP Core,有Verilog和VHDL两种语言版本,包含了FIFO和DMA两种实现方式,是开源的IP Core-Based on the wishbone bus SD Card IP Core, there are two language versions of Verilog and VHDL, including the FIFO and DMA implemented in two ways, is open source IP Core
Platform: | Size: 2271232 | Author: 张亚群 | Hits:

[VHDL-FPGA-Verilog] FPGA

Description: 结合FPGA和以太网传输的特点，设计了一套数据采集系统，应用FPGA的内部逻辑实现对ADC、SDRAM、网卡控制芯片DM9000的时序控制，以FPGA作为采集系统的核心，通过ADC，将采集到的数据存储到SDRAM中，以FIFO方式从SDRAM中读出数据，并将数据结果通过以太网接口传输到计算机-Combination of FPGA and Ethernet features, designed a data acquisition system, application FPGA' s internal logic to realize the ADC, SDRAM, LAN controller chip DM9000 timing control to capture FPGA as the core of the system, through the ADC, will be collected The data stored in SDRAM, the SDRAM in order to read data from the FIFO method, and data results to a computer via Ethernet interface
Platform: | Size: 388096 | Author: gdr | Hits:

[VHDL-FPGA-Verilog] fifo

Description: 在fpga中实现fifo，配合数码管显示，仅供学习参考-Realized in fpga fifo, with digital display, study and reference purposes only
Platform: | Size: 436224 | Author: 郝强 | Hits:

[VHDL-FPGA-Verilog] async-FIFO

Description: 采用VHDL实现异步的FIFO程序，是学习FPGA的重点内容-VHDL implementation using asynchronous FIFO procedures, the key elements to learn FPGA! !
Platform: | Size: 220160 | Author: yihoumei | Hits:

[VHDL-FPGA-Verilog] FPGA-Prototyping-by-VHDL-Examples---Xilinx-Sparta

Description: FPGA prototyping by VHDL examples include FIFO,RAM,ROM,filters, registers and others-FPGA prototyping by VHDL examples include FIFO,RAM,ROM,filters, registers and others
Platform: | Size: 16619520 | Author: Aleks | Hits:
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